1. Technical Field
The embodiments described herein relate to semiconductor circuit technologies, and more particularly, to a phase detection circuit that is used in a system requiring a phase comparison result.
2. Related Art
A conventional phase detection circuit can be configured using a flip-flop or a phase frequency detector. For example, referring to FIG. 1, a conventional phase detection circuit using a flip-flop includes a D flip-flop DFF and an inverter IV1.
The D flip-flop DFF is configured to receive a reference clock signal ‘REFCLK’ through the input terminal thereof and a feedback clock signal ‘FBCLK’ through the clock terminal thereof and to output an up signal ‘UP’ and a down signal ‘DN’ obtained by inverting the up signal ‘UP’ through the inverter IV1.
The feedback clock signal ‘FBCLK’ is a clock signal that is compared with the reference clock signal ‘REFCLK’ in a system using a phase detection circuit, for example, a locked loop circuit such as a DLL (delay locked loop) circuit or a PLL (phase locked loop) circuit.
If the phase of the reference clock signal ‘REFCLK’ is faster than the feedback clock signal ‘FBCLK’, as shown in FIG. 2a, the phase detection circuit of FIG. 1 outputs the up signal ‘UP’ at a high level. If the phase of the reference clock signal ‘REFCLK’ is slower than the feedback clock signal ‘FBCLK’, as shown in FIG. 2b, the phase detection circuit of FIG. 1 outputs the down signal ‘DN’ at a high level.
The phase detection circuit shown in FIG. 1 has two drawbacks. First, the phase detection circuit has a dead zone. That is to say, since the phase detection circuit has a low resolution, it cannot detect a phase difference below a certain level. The dead zone is directly associated with the setup and hold times of the flip-flop and may cause jitter in a system using the phase detection circuit.
Second, the phase detection circuit has a limited phase detection range. That is to say, the initial phase difference between two signals to be detected in the phases thereof must be in the range of π˜2π. If the initial phase difference is out of the range, an operation error can be caused in the system using the phase detection circuit shown in FIG. 1.
Therefore, in the system using the phase detection circuit shown in FIG. 1, a separate circuit must be added to make the phase difference between the two signals received by the phase detection circuit at an initial operation stage to be in the predefined range.
In a conventional phase detection circuit using a phase frequency detector, since the phase detection circuit has linear operation characteristics and both of an up signal ‘UP’ and a down signal ‘DN’ are output in short pulses, it is difficult to apply the phase detection circuit to a digital control type locked loop circuit.
For this reason, the phase detection circuit using a phase frequency detector has a limit in an application range in that the phase detection circuit must be configured together with a charge pump in an analog control type locked loop circuit, and the size of the phase detection circuit increases due to the presence of an additional circuit.